
Senior Hardware & Failure Analysis Engineer
Location: Kuala Lumpur, Malaysia
Led end-to-end system-level validation of SoC, DRAM, Flash and power regulators, enabling early defect detection and improving first-pass design success rate.
Improved validation cycle efficiency through structured test planning, execution and workflow optimization.
Performed electrical, functional, signal integrity and power validation using oscilloscopes, electronic loads and thermal testing to identify design and component-level issues.
Conducted structured root cause analysis (DOE, RCA) to resolve complex hardware failures, reducing recurring defects and improving product reliability.
Developed and executed comprehensive validation plans, ensuring coverage across electrical, thermal and functional requirements.
Collaborated cross-functionally with design, quality and sustaining teams to drive issue resolution and implement design improvements during NPI phase.
Reduced debug turnaround time by standardizing validation methodologies and improving test processes.
Mentored junior engineers in debugging techniques and failure analysis, strengthening overall team capability.
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